Common-Mode Voltage Mitigation Strategies Using Sigma–Delta Modulation in Five-Phase VSIs

Various sigma–delta ( $\Sigma$ notation="LaTeX">$\Delta$ ) modulation techniques for reducing the maximum peak-to-peak amplitude of common-mode voltage (CMV) by 80% in a five-phase, high-frequency source inverter (VSI) are proposed and evaluated this article. These based on choosing set vectors that limits CMV amplitude. Operating VSI under pulsewidth modulations (PWM) generates large number changes levels, which leads to currents (CMCs) conducted electromagnetic interferences (EMIs). The achieve following: 1) High-efficiency converter operation output with low total harmonic distortion (THD); 2) an reduction amplitude; 3) decrease transitions, thus CMCs; 4) EMI use single-loop double-loop modulators is analyzed means Matlab/Simulink PLECS simulations. implementation has been experimentally using five-phase silicon carbide semiconductors. In order demonstrate improved performance, results obtained compared those other PWM space vector also mitigate but lack improvements.